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Silicon Labs /EFR32FG23A011F512GM40 /GPIO_S /EUSART0_ROUTEEN

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Interpret as EUSART0_ROUTEEN

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31282724232019161512118743000000000000000000000000000000000000000000 (CSPEN)CSPEN0 (RTSPEN)RTSPEN0 (RXPEN)RXPEN0 (SCLKPEN)SCLKPEN0 (TXPEN)TXPEN

Description

EUSART0 pin enable

Fields

CSPEN

CS pin enable control bit
RTSPEN

RTS pin enable control bit
RXPEN

RX pin enable control bit
SCLKPEN

SCLK pin enable control bit
TXPEN

TX pin enable control bit

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data